The packaging industry has adopted the widespread use of flip chip technology for high performance applications. In a typical flip chip package, a semiconductor die may be bumped with individual conducting pads over its entire area. These conducting pads may be connected to front side devices present on the same semiconductor die by, for example, through substrate vias (TSVs). The conducting pads on the semiconductor die may also be connected to corresponding conducting pads on a substrate (or, in a 2.5 D package, an interposer or, in a 3D package, another semiconductor die) using small solder balls, or bumps, such as controlled collapse chip connections (C4 connections). The conducting pads on the substrate may be connected to circuitry that routes the electrical signals to an array of conductors (ball grid arrays (BGA)), column grid arrays (CGA) or land grid arrays (LGA)) to electrically connect to a printed circuit board.
A bonding pad, for example a C4 pad, may be formed on a back side of a semiconductor wafer after the back side has been thinned to expose vias, for example TSVs. The C4/bonding pad may be formed by depositing a conductive material, typically a metal such as copper, over the exposed bottom surface of the TSV and the back side of the semiconductor wafer.
This technique of forming bonding pads may result in a substantially flat interface between the semiconductor wafer/TSV and the bonding pad. While the flat interface may provide a continuous connection between the TSV and the bonding pad, it may be subject to delamination and separation during fluctuations in temperature of the flip chip (e.g., post chip join cool down). Differences in the coefficients of thermal expansion of the materials that make up the semiconductor wafer, the TSV, and the bonding pad, as well as mechanical stresses resulting from chip stacking, may cause the bonding pad to separate from the semiconductor wafer and the TSV. This separation may cause problems with electrical connections and reliability in the flip chip.